1. Field of the Invention
The present invention relates to an external test auxiliary device to be used for testing a semiconductor device, and more particularly, to an external auxiliary device suitable for improving measurement performance of LSI test equipment (called a xe2x80x9ctesterxe2x80x9d) and for expanding the function of the tester.
2. Description of the Background Art
In relation to a system LSI; that is, an LSI consisting of a single chip or a combination of chips into which a plurality of circuit modules are functionally placed, hybridization of digital circuits and analog circuits has been pursued. In order to cope with such a situation, testers capable of handling a mixed signal; i.e., a mixed signal consisting of an analog signal and a digital signal, have been developed. These testers have high-performance specifications and are usually expensive.
A conceivable another solution for handling the mixed signal is testing of a system LSI utilizing an existing low-cost tester; e.g., a tester for a logic LSI. Use of such a method is likely to raise problems in a characteristics test of an analog circuit for which higher precision is pursued; more specifically, in a characteristics test pertaining to a digital-to-analog converter (DAC) or analog-to-digital converter (ADC).
FIG. 11 is a block diagram for describing one example of a related-art method for testing characteristics of a DAC incorporated in a semiconductor device under test (hereinafter simply called a xe2x80x9cDUTxe2x80x9d). As shown in FIG. 11, reference numeral 1 designates a tester; and 10 designates a CPU provided in the tester 1. Further, reference numeral 2 designates a DUT. The DUT 2 has a DAC 3, an output section 4, and a CPU 5.
A digital signal 7 output from the tester 1 is supplied to the DAC 3 of the DUT 2. The digital signal 7 is converted into an analog signal by means of the DAC 3, and the analog signal is supplied to the output section 4. An analog signal 8 output from the output section 4 is supplied to RAM 11 after having been converted into a digital signal 9 by means of an ADC 6 provided outside the DUT 3.
A digital signal 7 identical with that supplied to the DUT 2 and a control signal 12 for controlling the operation of the RAM 11 (i.e., an address signal or a read/write signal) are supplied to the RAM 11 from the tester 1. The digital signal 7 and the digital signal 9 generated from the former are recorded in the RAM 11. After all tests to be conducted have been completed, record data pertaining to the tests are uploaded to the tester 1 as a digital signal 13. The tester 1 analyzes the thus-uploaded digital signal 13, thereby determining whether or not the DAC 3 of the DUT 2 is performing digital-to-analog conversion operation appropriately.
As mentioned above, according to the test method shown in FIG. 11, although the tester 1 has no function of handling an analog signal, the tester 1 can suitably conduct a test of the DAC 3 provided in the DUT 2.
However, when the test circuit shown in FIG. 11 is constituted through use of a popular tester, a plurality of connection elements; specifically, a DUT board on which the DUT 2 is to be mounted and a cable for connecting the DUT board to the tester 1, are provided in a pathway from a measurement device provided in the tester 1 to the DUT 2. Further, a long signal path is established between the measurement device provided in the tester 1 and the DUT 2. These connection elements and/or the long signal path account for occurrence of noise and deteriorate precision of measurement performed during a test.
Under the test method shown in FIG. 11, the digital signals 7 and 13 and the control signal 12 must be exchanged between the tester 1 and the RAM 11. Under this method, a plurality of pin electronics provided on the tester 1 are occupied for testing a single DUT 2. In this regard, the related-art test method suffers a great disadvantage as a method of simultaneously testing a plurality of semiconductor devices.
The related-art method further requires the tester 1 to perform all processing operations required for testing the DUT 2. For this reason, processing speed of the tester 1 cannot be improved. Moreover, the test method shown in FIG. 11 requires uploading of measurement data accumulated in the RAM 11 to the tester 1 after completion of a desired test. In this way, the related-art test method is not necessarily suitable for testing the DUT 2 at high speed.
The present invention has been conceived to solve these drawbacks and is aimed at providing an external test auxiliary device which can increase the processing speed of a tester to be used for testing a semiconductor device and expand the functions of the tester, which is less susceptible to influence of noise, and which enables high-speed testing of a semiconductor device.
The above objects of the present invention are achieved by an external test auxiliary device described below. The device includes a connector having a plurality of terminals. The connector is mounted on a BOST (built-off self-test) board substrate. An external self-test circuit is also formed on the BOST board substrate. The external self-test circuit includes a test signal transmission section which transmits a predetermined test signal to a specific terminal provided in the connector on the basis of a control signal input from the specific terminal provided in the connector. The external self-test circuit also includes a response signal receiving section which, in response to the test signal, receives a response signal input to a specific terminal provided in the connector. Further, the external self-test circuit includes a signal analysis section which analyzes the response signal, thereby determining whether or not the signal is an appropriate signal as well as a result signal transmission section which transmits, to a specific terminal provided in the connector, a test result signal representing whether or not the response signal is appropriate.
The above objects of the present invention are also achieved by an external test auxiliary device described below. The device includes a DUT (device under test) socket on which a semiconductor device under test is to be mounted. The DUT socket is mounted on a DUT board substrate. An external self-test circuit formed on the DUT board substrate. The DUT board substrate includes a plurality of connection terminals for establishing an electrical connection with a plurality of pins provided on a test head of a semiconductor tester. The DUT board substrate also includes a circuit element for establishing a desired electrical connection between the plurality of connection terminals, terminals of the DUT socket, and a plurality of circuit terminals of the external self-test circuit. The self-test circuit includes a test signal transmission section which transmits a predetermined test signal to a specific circuit terminal in accordance with a control signal input by way of a specific circuit terminal. The self-test circuit also includes a response signal receiving section for receiving, in response to the test signal, a response signal input to a specific circuit terminal. The self-test circuit further includes a signal analysis section which analyzes the response signal and determines whether or not the signal is an appropriate signal as well as a result signal transmission section for transmitting, to a specific circuit terminal, a test result signal representing whether or not the response signal is appropriate.
The above objects of the present invention are further achieved by an external test auxiliary device described below. The device includes a probe card having a plurality of probes to be brought into contact with a semiconductor wafer under test. An external self-test circuit is formed on the probe card. The probe card includes a plurality of connection terminals for establishing an electrical connection with a plurality of pins provided on a test head of a semiconductor tester. The prove card also includes a circuit element for establishing a desired electrical connection between the plurality of connection terminals, the plurality of terminals of the probe, and the plurality of circuit terminals of the external self-test circuit. The self-test circuit includes a test signal transmission section which transmits a predetermined test signal to a specific circuit terminal in accordance with a control signal input by way of a specific circuit terminal. The self-test circuit also includes a response signal receiving section for receiving, in response to the test signal, a response signal input to a specific circuit terminal. The self-test circuit further includes a signal analysis section which analyzes the response signal and determines whether or not the signal is an appropriate signal as well as a result signal transmission section for transmitting, to a specific circuit terminal, a test result signal representing whether or not the response signal is appropriate.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.